共 50 条
- [41] Design of CNFET full adder with mirror structure [J]. WIRELESS COMMUNICATION AND SENSOR NETWORK, 2016, : 1019 - 1024
- [42] Asynchronous Design of Energy Efficient Full Adder [J]. 2013 INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATION AND INFORMATICS, 2013,
- [43] OPTIMIZED LOW POWER FULL ADDER DESIGN [J]. 2017 INTERNATIONAL CONFERENCE ON NETWORKS & ADVANCES IN COMPUTATIONAL TECHNOLOGIES (NETACT), 2017, : 86 - 89
- [44] Multiple Threshold CVSL Full Adder Design [J]. PROCEEDINGS OF THE 2019 6TH INTERNATIONAL CONFERENCE ON COMPUTING FOR SUSTAINABLE GLOBAL DEVELOPMENT (INDIACOM), 2019, : 74 - 77
- [45] A new low-voltage CMOS 1-bit full adder for high performance applications [J]. 2002 IEEE ASIA-PACIFIC CONFERENCE ON ASIC PROCEEDINGS, 2002, : 21 - 24
- [46] A high-speed domino CMOS full adder driven by a new unified-BiCMOS inverter [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 452 - 455
- [47] Optimization of Hybrid CMOS Designs Using a New Energy Efficient 1 Bit Hybrid Full Adder [J]. PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON COMMUNICATION AND ELECTRONICS SYSTEMS (ICCES 2018), 2018, : 905 - 908
- [48] A High Speed Low Noise CMOS Dynamic Full Adder cell [J]. 2013 INTERNATIONAL CONFERENCE ON CIRCUITS, CONTROLS AND COMMUNICATIONS (CCUBE), 2013,
- [49] PERFORMANCE OF CMOS TERNARY FULL ADDER AT LIQUID-NITROGEN TEMPERATURE [J]. CRYOGENICS, 1995, 35 (09) : 599 - 605
- [50] Low-voltage low-power CMOS full adder [J]. IEE PROCEEDINGS-CIRCUITS DEVICES AND SYSTEMS, 2001, 148 (01): : 19 - 24