A SPACE-EFFICIENT SHORT-FINDING ALGORITHM

被引：0
|
作者：
SU, SL [1 ]
BARRY, CH [1 ]
LO, CY [1 ]
机构：
[1] AT&T BELL LABS, ALLENTOWN, PA 18103 USA
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1994年 / 13卷 / 08期
关键词：
Algorithms - Computer applications - Computer workstations - Critical path analysis - Data storage equipment - Electric fault location - Geometry - Graph theory - Redundancy - Response time (computer systems) - Theorem proving - VLSI circuits;
D O I：
10.1109/43.298043
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A common method of locating electrical shorts in VLSI layouts is to build a connectivity graph of the shorted net and then find the shortest path between the two offending signals. The memory requirement of this method is proportional to the size of the net, which can be quite large. This paper presents a dynamic graph construction algorithm that significantly reduces the peak memory requirement. The algorithmic framework allows continuous trade-offs between run times and memory requirements.
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页码：1065 / 1068
页数：4
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