THE IMPLEMENTATION OF DIGITAL ECHO CANCELLATION IN CODECS

被引：1

作者：

FRIEDMAN, V ^{[1
]}

KHOURY, JM ^{[1
]}

THEOBALD, M ^{[1
]}

GOPAL, VP ^{[1
]}

机构：

[1] AT&T BELL LABS,NAPERVILLE,IL 60540

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 04期

关键词：

D O I：

10.1109/4.58290

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The architecture of a codec in which the echo cancellation is done in two stages—an analog hybrid to reduce the echo level at the input of the A/D converter and a programmable digital balance filter—is presented. The design problems connected with this architecture, such as the signal-to-noise performance of the A/D converter and the limiting effects of the variation of the analog components on the echo cancellation performance of the device and on the structure of the digital balance filters, are discussed. These results were used in the design of a single-power-supply CMOS device implemented in 1.5-µm technology using ∑Δ modulation techniques for A/D and D/A conversion. Its echo cancellation performance is sufficiently high, such that only one set of coefficients per national standard is necessary. © 1990 IEEE

引用

页码：979 / 986

页数：8

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