This article considers programmable logic arrays as a typical model Errors in diagnostic responses that result from single faults are used to construct a signature analyzer that can detect all such errors. Order considerations are used to prove a number of general assertions on the parameters of analyzers; these propositions generalize directly to the case of multiple faults. Techniques for using these considerations and conclusions in applications to combinational circuits of an arbitrary nature are indicated.
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East China Normal Univ, Sch Comp Sci & Software Engn, Shanghai Key Lab Trustworthy Comp, Shanghai 200062, Peoples R ChinaEast China Normal Univ, Sch Comp Sci & Software Engn, Shanghai Key Lab Trustworthy Comp, Shanghai 200062, Peoples R China
Li, Chengju
Ding, Cunsheng
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Hong Kong Univ Sci & Technol, Dept Comp Sci & Engn, Kowloon, Hong Kong, Peoples R ChinaEast China Normal Univ, Sch Comp Sci & Software Engn, Shanghai Key Lab Trustworthy Comp, Shanghai 200062, Peoples R China
Ding, Cunsheng
Li, Shuxing
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Hong Kong Univ Sci & Technol, Dept Math, Kowloon, Hong Kong, Peoples R ChinaEast China Normal Univ, Sch Comp Sci & Software Engn, Shanghai Key Lab Trustworthy Comp, Shanghai 200062, Peoples R China