PIPELINE RING DATA-FLOW ARCHITECTURE FOR SOLVING LARGE ITERATIVE STRUCTURES

The paper reports on the progress of the prototyping of a novel iterative structure solver: the York Stream Machine. The York Stream Machine has a pipeline ring data-flow architecture. The processing elements in the architecture are FPGA (field programmable gate array) devices which are capable of implementing directly many register or combinatorial functions. This paper will highlight: (i) the network topology, (ii) the processing element architecture, (iii) the microinstruction generation techniques and (iv) the method employed by the Stream Machine to solve iterative algorithms. It will also describe the Stream Talk compiler developed to support the Stream Machine. The Stream Talk compiler takes as input a nested loop program expressed in an imperative syntax. It then constructs an intermediate task graph representation of its computation and maps the computation onto the pipeline ring structure. Encouraging speedups are demonstrated when the compiler is applied to some common nested loop kernels. The long term objective of the Stream Machine project is to demonstrate that by parallelising iterations in an algorithm over a pipeline ring and using hardware accelerating devices like FPGAs as processing elements, very high performances can be achieved.