2-D SYSTOLIC ARRAYS FOR REALIZATION OF 2-D CONVOLUTION

被引:4
|
作者
KWAN, HK
OKULLOOBALLA, TS
机构
[1] SINGAPORE POLYTECH,DEPT ELECTR & COMMUN ENGN,SINGAPORE 0513,SINGAPORE
[2] UNIV HONG KONG,HONG KONG,HONG KONG
来源
关键词
D O I
10.1109/31.45721
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, an image is regarded as a 2-D array of pixels and is processed by a 2-D array architecture. The image can be acquired in the usual manner by a raster scan method which produces a 1-D array of pixels at real-time video rates. The two 2-D systolic arrays for a 2-D convolver presented have an architecture which accepts this 1-D array of pixels and processes them in a 2-D array of simple processors. This high degree of parallelism is achieved through matrix-vector formulations of 2-D convolution. One array has a serial input, a serial output, and uses a minimum number of multipliers; while the other array has parallel inputs, parallel outputs, and is suitable for high-speed processing using slow processing elements. Both arrays are modular with nearest neighbor communications and are suitable for VLSI implementation. In addition, the algorithm for 2-D convolution presented here explicitly takes into account the boundary conditions. This feature allows a large image to be partitioned so that each partition may be processed by independent 2-D convolvers. It is then possible to process only a specified section of the image or carry out high-speed parallel processing using as many 2-D convolvers as are available. © 1990 IEEE
引用
收藏
页码:267 / 273
页数:7
相关论文
共 50 条