AUTOMATIC IMPLEMENTATION OF FIR FILTERS ON FIELD-PROGRAMMABLE GATE ARRAYS

被引：3

作者：

MOHANAKRISHNAN, S

EVANS, JB

机构：

[1] Telecommunications and Information Sciences Laboratory, Department of Electrical Engineering and Computer Science, University of Kansas, Lawrence

来源：

IEEE SIGNAL PROCESSING LETTERS | 1995年 / 2卷 / 03期

关键词：

D O I：

10.1109/97.372915

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This letter describes a CAD system for automatic implementation of FIR filters on Xilinx field programmable gate arrays (FPGA). Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space, and implements it on FPGA chips. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters that were implemented is presented.

引用

页码：51 / 53

页数：3

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