A MICROPROGRAMMABLE REAL-TIME VIDEO SIGNAL PROCESSOR (VSP) LSI

被引:9
|
作者
YAMASHINA, M
ENOMOTO, T
KUNIO, T
TAMITANI, I
HARASAKI, H
NISHITANI, T
SATOH, M
KIKUCHI, K
机构
[1] NEC CORP,C&C SYST RES LABS,COMMUN RES LAB,SAGAMIHARA,KANAGAWA 229,JAPAN
[2] NEC CORP,DIV TRANSMISS,DEPT BASIC CIRCUIT DEV,SAGAMINARA,KANAGAWA 229,JAPAN
[3] NEC CORP,DIV SYST LSI DEV,SAGAMIHARA,KANAGAWA 229,JAPAN
关键词
COMPUTER ARCHITECTURE - Microprogramming - COMPUTER SYSTEMS; DIGITAL - Parallel Processing - SIGNAL PROCESSING;
D O I
10.1109/JSSC.1987.1052862
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2. 5- mu m CMOS and double-layer metallization technology, has an area of 9. 91 multiplied by 9. 50 mm**2 and contains about 48,000 MOSFETs. It operates at a clock frequency of 14. 3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.
引用
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页码:1117 / 1123
页数:7
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