GPU Accelerated Belief Propagation Decoding of Non-Binary LDPC Codes with Parallel and Sequential Scheduling

Low-Density Parity-Check (LDPC) codes are very powerful channel coding schemes with a broad range of applications. The existence of low complexity (i.e., linear time) iterative message passing decoders with close to optimum error correction performance is one of the main strengths of LDPC codes. It has been shown that the performance of these decoders can be further enhanced if the LDPC codes are extended to higher order Galois fields, yielding so called non-binary LDPC codes. However, this performance gain comes at the cost of rapidly increasing decoding complexity. To deal with this increased complexity, we present an efficient implementation of a signed-log domain FFT decoder for non-binary irregular LDPC codes which exploits the inherent massive parallelization capabilities of message passing decoders. We employ Nvidia’s Compute Unified Device Architecture (CUDA) to incorporate the available processing power of state-of-the-art Graphics Processing Units (GPUs). Furthermore, we present a CUDA implementation of the signed-log domain FFT decoder using the so-called layered update rule, in which check nodes are updated one after another. This sequential updating of nodes has been shown to converge about twice as fast as the traditional flooding scheme. To achieve a high speedup of the layered CUDA implementation, we employ quasi-cyclic non-binary LDPC codes since they allow to update multiple neighboring check nodes in parallel without any performance loss.