Reconfigurable testbed for interference cancellation in DS-CDMA systems

Interference cancellation techniques for direct-sequence code division multiple access (DS-CDMA) systems have the potential to provide significant capacity gains over conventional matched filter receivers. The complexity of the signal processing algorithms for interference cancellation often requires processing speeds that are beyond that of current digital signal processor (DSP) technology. In this paper, we show that this difficulty can be overcome by partitioning the algorithmic functionality into two core technologies (field programmable gate arrays [FPGA] and DSP devices) based on processing speed requirements. We give implementation proofs via a testbed that allows a dynamic reconfiguration among constituent receivers being considered. Experimental results on the performance of the receivers are presented.