Reconfigurable testbed for interference cancellation in DS-CDMA systems

被引：0
|
作者：
Seskar I. [1 ]
Mandayam N.B. [1 ,2 ,3 ]
Hatrack P. [1 ,4 ,5 ,6 ]
机构：
[1] Wireless Info. Network Laboratory, Rutgers University, Piscataway, NJ 08854-8060
[2] Indian Institute of Technology, Kharagpur
[3] Rice University, Houston, TX
[4] George Washington University, Washington, D.C.
[5] Rutgers University, New Brunswick, N.J.
[6] Interactive Media Group, Sarnoff Corporation, Princeton, N.J.
来源：
International Journal of Wireless Information Networks | 1999年 / 6卷 / 1期
关键词：
RECONFIGURABLE RECEIVERS; SOFTWARE DEFINED RADIO ARCHITECTURES; INTERFERENCE CANCELLATION;
D O I：
10.1023/A:1018879216442
中图分类号：
学科分类号：
摘要：
Interference cancellation techniques for direct-sequence code division multiple access (DS-CDMA) systems have the potential to provide significant capacity gains over conventional matched filter receivers. The complexity of the signal processing algorithms for interference cancellation often requires processing speeds that are beyond that of current digital signal processor (DSP) technology. In this paper, we show that this difficulty can be overcome by partitioning the algorithmic functionality into two core technologies (field programmable gate arrays [FPGA] and DSP devices) based on processing speed requirements. We give implementation proofs via a testbed that allows a dynamic reconfiguration among constituent receivers being considered. Experimental results on the performance of the receivers are presented.
引用
收藏
页码：37 / 47
页数：10
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