Characterization of single-event multiple cell upsets in a custom SRAM in a 65 nm triple-well CMOS technology

In this paper, the characterization of single event multiple cell upsets (MCUs) in a custom SRAM is performed in a 65 nm triple- well CMOS technology, and O (linear energy transfer (LET) = 3.1 MeV cm2/mg), Ti (LET = 22.2 MeV cm2/mg) and Ge (LET = 37.4 MeV cm2/mg) particles are employed. The experimental results show that the percentage of MCU events in total upset events is 71.11%, 83.47% and 85.53% at O, Ti and Ge exposures. Moreover, due to the vertical well isolation layout, 100% (O), 100% (Ti) and 98.11% (Ge) MCU cluster just present at one or two adjacent columns, but there are still 4 cell upsets in one MCU cluster appearing on the same word wire. The characterization indicates that MCUs have become the main source of soft errors in SRAM, and even though combining the storage array interleaving distance (ID) scheme with the error detection and correction (EDAC) technique, the MCUs cannot be completely eliminated, new radiation hardened by design techniques still need to be further studied.