A CMOS Voltage Comparator with Rail-to-Rail Input-Range

被引：0
|
作者：
Wei-Shang Chu
K. Wayne Current
机构：
[1] University of California,Electrical and Computer Engineering Department
来源：
Analog Integrated Circuits and Signal Processing | 1999年 / 19卷
关键词：
CMOS continuous-time voltage comparator; rail-to-rail input range;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 μm×221 μm in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).
引用
收藏
页码：145 / 149
页数：4
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