A rail-to-rail input-range CMOS voltage comparator

被引：0

作者：

Chu, WS ^{[1
]}

Current, KW ^{[1
]}

机构：

[1] Univ Calif Davis, Dept Elect & Comp Engn, Livermore, CA 95616 USA

来源：

40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

A simple new continuous-time CMOS comparator circuit with supply-to-supply input common-mode range is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit requires an area of 416 mu m x 221 mu m in a MOSIS 2-micron CMOS technology. It operates at 3V and requires between 0.5 and 1.3mA. Delays of between 54 and 282ns have been measured.

引用

页码：160 / 163

页数：2

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