A 14-bit 500-MS/s DAC with 211-MHz 70 dB SFDR bandwidth using TRI-DEMRZ

Time-relaxed interleaving dynamic element matching return-to-zero (TRI-DEMRZ) is proposed and verified in this paper to improve the spurious-free dynamic range (SFDR) of current-steering digital-to-analog converters (DACs). It incorporates time-relaxed interleaving (TRI), return-to-zero, and the dynamic-element-matching techniques, in a way that fosters the strength of each technique. As analyzed in this paper, merits beyond the combination of these techniques could be achieved. Firstly, TRI-DEMRZ provides a new dimension in the space domain, rather than the time domain, to explore the methods of mitigating nonlinear switching distortions. Secondly, this paper proves that, the image tone caused by typical channel mismatches between interleaved sub-DACs can be randomized into noise with TRI-DEMRZ. Circuit simulations and analysis are provided. An experimental 14-bit 500-MS/s current-steering DAC in 65 nm CMOS has been fabricated and measured, showing 81 dB SFDR at 5.5 MHz and more than 70 dB SFDR up to 211 MHz bandwidth. The SFDR improvement achieved by TRI-DEMRZ is more than 10 dB, which further verifies the effectiveness of TRI-DEMRZ.