Scenario-based verification in presence of variability using a synchronous approach

被引：0
|
作者：
Jean-Vivien Millo
Frédéric Mallet
Anthony Coadou
S. Ramesh
机构：
[1] Aoste team (INRIA/I3S/CNRS/UNS),INRIA Sophia
[2] University of Nice Sophia Antipolis,Antipolis
[3] GM Technical Center India,Global General Motors R&D, India Science Lab
来源：
Frontiers of Computer Science | 2013年 / 7卷
关键词：
Esterel; UML MARTE; scenario; verification; feature interaction; variability;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.
引用
收藏
页码：650 / 672
页数：22
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