Scenario-based verification in presence of variability using a synchronous approach

被引：1
|
作者：
Millo, Jean-Vivien [1 ]
Mallet, Frederic [2 ]
Coadou, Anthony [3 ]
Ramesh, S. [3 ]
机构：
[1] INRIA Sophia Antipolis, Aoste Team, INRIA, UNS,CNRS,I3S, F-06560 Sophia Antipolis, France
[2] Univ Nice Sophia Antipolis, F-06900 Sophia Antipolis, France
[3] GM Tech Ctr India, Global Gen Motors R&D, India Sci Lab, Bangalore 560066, Karnataka, India
来源：
FRONTIERS OF COMPUTER SCIENCE | 2013年 / 7卷 / 05期
关键词：
Esterel; UML MARTE; scenario; verification; feature interaction; variability; MODEL CHECKING;
D O I：
10.1007/s11704-013-3094-6
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a new model of scenarios, dedicated to the specification and verification of system behaviours in the context of software product lines (SPL). We draw our inspiration from some techniques that are mostly used in the hardware community, and we show how they could be applied to the verification of software components. We point out the benefits of synchronous languages and models to bridge the gap between both worlds.
引用
收藏
页码：650 / 672
页数：23
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