An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.