Reliability Model for Multiple-Error Protected Static Memories

The problem of multi-cell upset (MCU) becomes a major issue in the nanometer SRAM chips. Various types of multi-bit error correction codes (MECC) have been developed to mitigate this problem. Proper selection of different parameters of each MECC scheme can lead to efficient encoder/decoder design. In this paper a semi-analytical model is presented which can estimate the memory failure probability (as well as mean time between failures (MTBF) and reliability) and can guide the system designers to select proper protection scheme for the system memories. The model was validated by comparison to simulation method (less than 3.1% estimation error) and a state of the art model (less than 2.9% estimation error). The impact of various parameters of four types of correction schemes is analyzed and a comparison of these coding schemes with respect to their capabilities to enhance memory reliability is performed.