Workload balancing in printed circuit board assembly

被引:0
|
作者
Stefan Emet
Timo Knuutila
Esa Alhoniemi
Michael Maier
Mika Johnsson
Olli S. Nevalainen
机构
[1] University of Turku,Department of Mathematics
[2] University of Turku,Department of Information Technology
[3] Valor Computerized Systems (Finland) Oy,undefined
关键词
Line balancing; Component placement machines; Printed circuit boards (PCB); Assembly optimization; Computer-aided process planning (CAPP);
D O I
暂无
中图分类号
学科分类号
摘要
Line balancing of a printed circuit board (PCB) assembly line is considered in the present paper. The production line consists of a number of machines for inserting electronic components on bare PCBs. The aim is to distribute the assembly operations of a single PCB type to the different machines in such a way that the throughput (i.e., the number of finished PCBs per time unit) of the line is maximized. We suppose that the total time for placements is a linear function of the number of component insertions performed by a machine. Effective mathematical formulations of the balancing problem are then available but previous models omit several aspects having an effect on the actual placement times. In particular, we extend an existing MILP formulation of the problem to consider the usage of feeder modules, precedence constraints among the placement operations, and duplication of frequently used components in several machines. We consider production lines consisting of several gantry-type placement machines. Unlike previous research, we applied standard optimization tools for solving the balancing problems. We then observed that the CPLEX-software was able to solve MILP formulations of 2- and 3-machine problems with up to 150 different component types and relatively large number of component placements (from 400 to 6,000). On the other hand, the running time was rather unstable so that heuristics are still needed for cases where exact methods fail.
引用
收藏
页码:1175 / 1182
页数:7
相关论文
共 50 条
  • [31] ELITE MACHINES FACILITATE PRINTED-CIRCUIT BOARD ASSEMBLY
    不详
    [J]. MACHINERY AND PRODUCTION ENGINEERING, 1974, 124 (3209): : 661 - 661
  • [32] Printed circuit board assembly test process and design for testability
    Nguyen, Thao
    Rezvani, Navid
    [J]. ISQED 2008: PROCEEDINGS OF THE NINTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, 2008, : 594 - 599
  • [33] Scheduling hybrid flowshops in printed circuit board assembly lines
    Jin, ZH
    Ohno, K
    Ito, T
    Elmaghraby, SE
    [J]. PRODUCTION AND OPERATIONS MANAGEMENT, 2002, 11 (02) : 216 - 230
  • [34] Precedence constrained TSP arising in printed circuit board assembly
    Duman, E
    Or, I
    [J]. INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 2004, 42 (01) : 67 - 78
  • [35] An efficient assembly sequencing heuristic for printed circuit board configurations
    Moyer, LK
    Gupta, SM
    [J]. JOURNAL OF ELECTRONICS MANUFACTURING, 1997, 7 (02): : 143 - 160
  • [36] PRINTED-CIRCUIT-BOARD ASSEMBLY PICKS UP ON AUTOMATION
    MANGIN, CH
    DAGOSTINO, S
    [J]. ELECTRONICS, 1984, 57 (01): : 171 - 174
  • [37] A planning and scheduling model for onsertion in printed circuit board assembly
    Ashayeri, J.
    Selen, W.
    [J]. EUROPEAN JOURNAL OF OPERATIONAL RESEARCH, 2007, 183 (02) : 909 - 925
  • [38] Setup reduction in printed circuit board assembly by efficient sequencing
    Narayanaswami, R
    Iyengar, V
    [J]. INTERNATIONAL JOURNAL OF ADVANCED MANUFACTURING TECHNOLOGY, 2005, 26 (03): : 276 - 284
  • [39] Modeling a printed circuit board assembly line using objects
    Narayanan, S
    Evans, J
    Bodner, D
    Sreekanth, U
    Govindaraj, T
    McGinnis, L
    Mitchell, C
    [J]. SIMULATION, 2000, 75 (5-6) : 287 - 300
  • [40] Setup reduction in printed circuit board assembly by efficient sequencing
    R. Narayanaswami
    V. Iyengar
    [J]. The International Journal of Advanced Manufacturing Technology, 2005, 26 : 276 - 284