Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

被引：0
|
作者：
Ruo-Shi Dong
Lei Zhao
Jia-Jun Qin
Wen-Tao Zhong
Yi-Chun Fan
Shu-Bin Liu
Qi An
机构：
[1] University of Science and Technology of China,State Key Laboratory of Particle Detection and Electronics
[2] University of Science and Technology of China,Department of Modern Physics
来源：
Nuclear Science and Techniques | 2021年 / 32卷
关键词：
Time-interleaved technique; High-speed A/D conversion; High bandwidth; Mismatch error correction;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The time-interleaved analog-to-digital conversion (TIADC) technique is an effective method for increasing the sampling rate in a waveform digitization system. In this study, a 20-Gsps TIADC system was designed. A wide-bandwidth performance was achieved by optimizing the analog circuits, and a sufficient effective number of bits (ENOB) performance guaranteed using the perfect reconstruction algorithm for mismatch error correction. The proposed system was verified by tests, and the results indicated that a − 3 dB bandwidth of 6 GHz and the ENOB performance of 8.7 bits at 1 GHz and 7.6 bits at 6 GHz were successfully achieved.
引用
收藏
相关论文
共 50 条
  • [41] On Blind Identification of Gain and Timing Mismatches in Time-Interleaved Analog-to-Digital Converters
    Saleem, Shahzad
    Vogel, Christian
    TSP 2010: 33RD INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND SIGNAL PROCESSING, 2010, : 151 - 155
  • [42] Adaptive Correction of Amplitude Noise for Time-Interleaved Photonic Analog-to-digital Converter
    Ye, Lei
    Wu, Guiling
    Su, Feiran
    Chen, Jianping
    2015 OPTO-ELECTRONICS AND COMMUNICATIONS CONFERENCE (OECC), 2015,
  • [43] Theoretical analysis on the sampling criteria for time-interleaved photonic analog-to-digital converters
    Chen, Jianping
    Su, Feiran
    Wu, Guiling
    REAL-TIME PHOTONIC MEASUREMENTS, DATA MANAGEMENT, AND PROCESSING, 2014, 9279
  • [44] A 12-bit 1-Msample/s Pipelined Analog-to-Digital Converter
    Yadav, Ashutosh
    Tripathi, Rahul Kumar
    Srivastava, Rajesh Kumar
    Rana, Parveen
    Jatana, H. S.
    Roy, J. N.
    JOURNAL OF SPACECRAFT TECHNOLOGY, 2009, 19 (01): : 9 - 17
  • [45] Digital background and blind calibration for clock skew error in time-interleaved analog-to-digital converters
    Camarero, D
    Naviner, JF
    Loumeau, P
    SBCCI2004:17TH SYMPOSIUM ON INTEGRATED CIRCUITS AND SYSTEMS DESIGN, PROCEEDINGS, 2004, : 228 - 232
  • [46] Design of a low-power 12-bit 1msps sar analog-to-digital converter
    Chun J.-I.
    Choi Y.-J.
    Ryu J.-Y.
    Journal of Institute of Control, Robotics and Systems, 2021, 27 (01) : 26 - 31
  • [47] Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver
    Tsai, Tsung-Heng
    Hurst, Paul J.
    Lewis, Stephen H.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2009, 56 (02) : 307 - 319
  • [48] All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters
    Chen, Shuai
    Wang, Luke
    Zhang, Hong
    Murugesu, Rosanah
    Dunwell, Dustin
    Carusone, Anthony Chan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2017, 25 (09) : 2552 - 2560
  • [49] An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters
    Gao, Jian
    Ye, Peng
    Zeng, Hao
    Song, Jinpeng
    Wei, Wentao
    Yang, Kuojun
    REVIEW OF SCIENTIFIC INSTRUMENTS, 2019, 90 (02):
  • [50] A background correction technique for timing errors in time-interleaved analog-to-digital converters.
    Iroaga, E
    Murmann, B
    Nathawad, L
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 5557 - 5560
12345