A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range.