Noise Determination in Differential Pair-Based Second Generation Current Conveyors

The aim of this paper is to give simple design guidelines for the noise evaluation in differential pair-based second generation current conveyors (CCIIs). Input noise voltage and current have been expressed in terms of some well known constants and MOS gm values, so allowing a very fast estimation of the noise level. The presented theory has been verified, as an example, on two fabricated low voltage low power CCII topologies. Theoretical values, simulations and on chip measurements are also shown and their good agreement confirms the validity of the presented idea.