A Constraint Satisfaction Approach to a Circuit Design Problem

被引:0
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作者
Jean-François Puget
Pascal van Hentenryck
机构
[1] Ilog SA,
[2] Brown University,undefined
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关键词
Global zero search; Electrical circuit; Transistor modelling; Interval methods; Branch and prune; Constraint satisfaction;
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摘要
A classical circuit-design problem from Ebers and Moll (1954) features a system of nine nonlinear equations in nine variables that is very challenging both for local and global methods. This system was solved globally using an interval method by Ratschek and Rokne (1993) in the box [0, 10]9. Their algorithm had enormous costs (i.e., over 14 months using a network of 30 Sun Sparc-1 workstations) but they state that ‘at this time, we know no other method which has been applied to this circuit design problem and which has led to the same guaranteed result of locating exactly one solution in this huge domain, completed with a reliable error estimate’. The present paper gives a novel branch-and-prune algorithm that obtains a unique safe box for the above system within reasonable computation times. The algorithm combines traditional interval techniques with an adaptation of discrete constraint-satisfaction techniques to continuous problems. Of particular interest is the simplicity of the approach.
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页码:75 / 93
页数:18
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