A Novel Multiple-Valued CMOS Flip-Flop Employing Multiple-Valued Clock

被引：0
|
作者：
Yin-Shui Xia
Lun-Yao Wang
A. E. A. Almaini
机构：
[1] Napier University,School of Engineering
[2] Ningbo University,School of Information and Engineering Science
来源：
Journal of Computer Science and Technology | 2005年 / 20卷
关键词：
CMOS; flip-flops; multiple-valued clock; multiple-valued logic;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A new CMOS quaternary D flip-flop is implemented employing a multiple-valued clock. PSpice simulation shows that the proposed flip-flop has correct operation. Compared with traditional multiple-valued flip-flops, the proposed multiple-valued CMOS flip-flop is characterized by improved storage capacity, flexible logic structure and reduced power dissipation.
引用
收藏
页码：237 / 242
页数：5
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