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- [2] Characterization of hermetic wafer-level Cu-Sn SLID bonding 2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
- [3] Wafer bonding using Cu-Sn intermetallic bonding layers MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2014, 20 (4-5): : 653 - 662
- [4] Optimization of Cu/Sn wafer-level bonding based upon intermetallic characterization 2012 4TH ELECTRONIC SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE (ESTC), 2012,
- [5] Systematic characterization of key parameters of hermetic wafer-level Cu-Sn SLID bonding 2013 EUROPEAN MICROELECTRONICS PACKAGING CONFERENCE (EMPC), 2013,
- [7] Cu/Sn SLID Wafer-level Bonding Optimization 2013 IEEE 63RD ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC), 2013, : 1531 - 1537
- [8] RESIDUAL STRESS IN SILICON CAUSED BY CU-SN WAFER-LEVEL PACKAGING PROCEEDINGS OF THE ASME INTERNATIONAL TECHNICAL CONFERENCE AND EXHIBITION ON PACKAGING AND INTEGRATION OF ELECTRONIC AND PHOTONIC MICROSYSTEMS, 2013, VOL 1, 2014,
- [9] High Temperature Pressure Sensor Using Cu-Sn Wafer Level Bonding 2015 IEEE SENSORS, 2015, : 1689 - 1692
- [10] Wafer bonding using Cu–Sn intermetallic bonding layers Microsystem Technologies, 2014, 20 : 653 - 662