Efficient FPGA architecture of optimized Haar wavelet transform for image and video processing applications

Discrete Wavelet Transform (DWT) is widely used in digital image and video processing due to its various advantages over other similar transform techniques. In this paper, efficient hardware architecture of Optimized Haar Wavelet Transform is proposed which is modeled using Optimized Kogge–Stone Adder/Subtractor, Optimized Controller, Buffer, Shifter and D_FF blocks. The existing Kogge–Stone Adder architecture is optimized by using Modified Carry Correction block which uses parallel architecture to reduce the computational delay. Similarly, the Controller block is optimized by using Clock Dividers and Reset Counter interdependently. To preserve the accuracy of the processed data, suitable size of intermediate bits in fractional format with the help of Q-notation is considered. The comparison results show that the proposed architecture performs better than existing ones concerning both hardware utilization and data accuracy.