Optimal dynamic range scaling of ΔΣ ADC using bias current estimation

In this paper, optimal dynamic range scaling of ΔΣ ADC using bias current estimation method is proposed. Generally, a different dynamic range scaling gives different feedback factor and effective load capacitance to each integrator in the ΔΣ ADC. It means that power consumption of each integrator strongly depends on the coefficient of the integrator. Therefore, the proposed method estimates which dynamic range scaling consumes the least power to achieve a given settling error. To verify the effectiveness of the proposed method, the noise coupled third order ΔΣ ADC having different dynamic scaling with transistor level opamps was simulated to compare the ADC performance.