Improved tri-state buffer in MOS current mode logic and its application

This paper presents a new topology to implement MOS current mode logic (MCML) tri-state buffer. The current source section of the available MCML tri-state buffer is modified in the proposed topology which improves output enable time and maintains the low power feature. The functionality of the proposed topology is verified through SPICE simulations by using 0.18 µm TSMC CMOS technology parameters. Its performance is compared with the available one for different values of bias current ranging from 50 to 200 µA. The delay decreases with increase in current and improvement in output enable time is visible throughout the current range. The impact of parameter variations at different design corners and width mismatch on the performance of both the proposed and the available tri-state buffers is also studied and similar variations are found. The significance of the improvement is demonstrated through the implementation of a tri-state buffer based edge triggered register, a key element in digital systems design.