Ring oscillators based on monolayer Graphene FET

A ring oscillator is an important circuit used to evaluate the performance limits of any digital technology. The advantages of Graphene field effect transistor (GFET) over current CMOS technologies make it a prominent candidate for future high-performance electronics. In this paper, a GFET model is implemented in Verilog-A, and GFET design and analysis of a ring oscillator are performed using advanced design system (ADS) tool. By using GFET ring oscillator, the designed circuit is simulated using a 0.18 µm GFET process in ADS environment. The results show that the power consumption is 9.98 mW, while the VCO generates 24.12 GHz at 1 V. The effect of Graphene channel length variations on the frequency span, power dissipation and phase noise of GFET ring oscillators are studied. The main performance characteristics of the ring oscillator are compared with CMOS technology. It is shown that a GFET ring oscillator gives a higher oscillation frequency and has more power dissipation.