Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline Voltage Swing

We propose an ultra-low power memory design method based on the ultra-low (∼\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\sim $$\end{document}0.2 V) write-bitline voltage swing to reduce the write power dissipation for read-decoupled SRAM (RD-SRAM) cells. By keeping the write bitlines at ground level (0 V) during standby and charging them to a low voltage VL\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$V_\mathrm{L}$$\end{document} (∼\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\sim $$\end{document}0.2 V) during write operations, the power dissipation for the write bitlines is greatly reduced (0.2 V/VDD)2×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$V_\mathrm{DD})^{ 2 }\,\times $$\end{document} 100 %) due to reduced voltage swing (from VDD\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$V_\mathrm{DD }$$\end{document} = 1.2 to 0.2 V) on the write bitlines. The proposed method is applicable to both dual-voltage and single-voltage operations. We analyze the proposed ultra-low write-bitline voltage swing method and investigate its reliability based on 10K Monte-Carlo simulations. We further verify the functionality and performance of our proposed design through measurements on the fabricated prototypes based on the 65 nm CMOS process. By means of a 256×64\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$256 \times 64$$\end{document} bit RD-SRAM memory implementation, we show that our proposed method reduces 87 % write power dissipation when compared to a conventional design.