Hardware Generation of Random Single Input Change Test Sequences

被引：0
|
作者：
R. David
P. Girard
C. Landrault
S. Pravossoudovitch
A. Virazel
机构：
[1] Laboratoire d'Automatique de Grenoble (INPG-CNRS-UJF),Laboratoire d'Informatique, de Robotique et de Microélectronique de Montpellier
[2] CNRS/Université Montpellier II,undefined
来源：
Journal of Electronic Testing | 2002年 / 18卷
关键词：
random testing; hardware; generation; test sequence; single input change;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
The combination of higher quality requirements and sensitivity of high performance circuits to delay defects has led to an increasing emphasis on delay testing of VLSI circuits. As delay testing using external testers requires expensive ATE, built-in self test (BIST) is an alternative technique that can significantly reduce the test cost.
引用
收藏
页码：145 / 157
页数：12
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