Single-crystalline ZnO sheet Source-Gated Transistors

被引:0
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作者
A. S. Dahiya
C. Opoku
R. A. Sporea
B. Sarvankumar
G. Poulin-Vittrant
F. Cayrel
N. Camara
D. Alquier
机构
[1] Université François Rabelais de Tours,
[2] CNRS,undefined
[3] GREMAN UMR 7347,undefined
[4] 16,undefined
[5] rue pierre et marie Curie,undefined
[6] Advanced Technology Institute,undefined
[7] University of Surrey,undefined
[8] Université François Rabelais de Tours,undefined
[9] INSA-CVL,undefined
[10] CNRS,undefined
[11] GREMAN UMR 7347,undefined
[12] 3 rue de la Chocolaterie,undefined
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摘要
Due to their fabrication simplicity, fully compatible with low-cost large-area device assembly strategies, source-gated transistors (SGTs) have received significant research attention in the area of high-performance electronics over large area low-cost substrates. While usually based on either amorphous or polycrystalline silicon (α-Si and poly-Si, respectively) thin-film technologies, the present work demonstrate the assembly of SGTs based on single-crystalline ZnO sheet (ZS) with asymmetric ohmic drain and Schottky source contacts. Electrical transport studies of the fabricated devices show excellent field-effect transport behaviour with abrupt drain current saturation (IDSSAT) at low drain voltages well below 2 V, even at very large gate voltages. The performance of a ZS based SGT is compared with a similar device with ohmic source contacts. The ZS SGT is found to exhibit much higher intrinsic gain, comparable on/off ratio and low off currents in the sub-picoamp range. This approach of device assembly may form the technological basis for highly efficient low-power analog and digital electronics using ZnO and/or other semiconducting nanomaterial.
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