Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS

被引:0
|
作者
Antaryami Panigrahi
Abhipsa Parhi
机构
[1] CIT-Kokrajhar,Department of Electronics & Communication Engineering
[2] BBEC-Kokrajhar,Department of Electrical Engineering
来源
Analog Integrated Circuits and Signal Processing | 2017年 / 92卷
关键词
CMOS amplifier; OTA; Voltage combiner;
D O I
暂无
中图分类号
学科分类号
摘要
A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a Gm boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of 2VV\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$2\,\frac{{\text{V}}}{{\text{V}}}$$\end{document}, this voltage combiner can produce gain more than 5VV\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$5\,\frac{{\text{V}}}{{\text{V}}}$$\end{document}. So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than 55∘\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$55^{\circ }$$\end{document} for a typical load of 10 pF. The input referred noise is 150μV/Hz\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}$$\end{document} at 10 Hz and slew rate 0.02V/μs\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$0.02\,{\text{V}}{/}\upmu{\text{s}}$$\end{document} for 10 pF load.
引用
收藏
页码:159 / 165
页数:6
相关论文
共 7 条
  • [1] Design of 0.5 V voltage-combiner based OTA with 60 dB gain 250 kHz UGB in CMOS
    Panigrahi, Antaryami
    Parhi, Abhipsa
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 2017, 92 (01) : 159 - 165
  • [2] A 0.5V Voltage-Combiner based Pseudo Differential OTA design in CMOS using Weakly inverted Transistors
    Panigrahi, Antaryami
    Parhi, Abhipsa
    PROCEEDINGS OF 2016 IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2016, : 144 - 148
  • [3] A 1.8 V Gain Enhanced Fully Differential Doubly-Recycled Cascode OTA with 100 dB Gain 200 MHz UGB in CMOS
    Panigrahi, Antaryami
    Parhi, Abhipsa
    VLSI DESIGN AND TEST, 2017, 711 : 646 - 656
  • [4] A 0.2V 492nW VCO-based OTA with 60kHz UGB and 207μVRMS Noise
    Kalani, Sarthak
    Bertolini, Alessandro
    Richelli, Anna
    Kinget, Peter R.
    2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2017,
  • [5] A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process
    Ferreira, Luis H. C.
    Sonkusale, Sameer R.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (06) : 1609 - 1617
  • [6] A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process
    Ferreira, Luis H. C.
    Sonkusale, Sameer R.
    2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2014, : 1881 - 1884
  • [7] Design of a 0.5 V op-amp based on CMOS inverter using floating voltage sources
    Wang, Jun
    Lee, Tuck-Yang
    Kim, Dong-Gyou
    Matsuoka, Toshimasa
    Taniguchi, Kenji
    IEICE TRANSACTIONS ON ELECTRONICS, 2008, E91C (08) : 1375 - 1378