A gain enhancement technique for a pseudo differential OTA based on voltage combiner, suitable for sub-1 V supply is presented in this letter. The proposed technique uses a Gm boosted voltage combiner. Unlike the typical voltage combiner which has an approximated gain of 2VV\documentclass[12pt]{minimal}
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\begin{document}$$2\,\frac{{\text{V}}}{{\text{V}}}$$\end{document}, this voltage combiner can produce gain more than 5VV\documentclass[12pt]{minimal}
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\begin{document}$$5\,\frac{{\text{V}}}{{\text{V}}}$$\end{document}. So it help us achieve nearly 60 dB DC gain with 250 kHz UGB for the pseudo differential OTA at a capacitive load of 10 pF. Power dissipation is very low i.e. 716 nW at supply of 0.5 V. So as to facilitate maximum swing at 0.5 V supply and lower the power consumption, MOS transistors are biased in weak/moderate inversion. The OTA is designed in standard 45 nm CMOS process. Phase margin of is more than 55∘\documentclass[12pt]{minimal}
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\begin{document}$$55^{\circ }$$\end{document} for a typical load of 10 pF. The input referred noise is 150μV/Hz\documentclass[12pt]{minimal}
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\begin{document}$$150\,\upmu {\text{V}}{/}\sqrt{{\text{Hz}}}$$\end{document} at 10 Hz and slew rate 0.02V/μs\documentclass[12pt]{minimal}
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\begin{document}$$0.02\,{\text{V}}{/}\upmu{\text{s}}$$\end{document} for 10 pF load.