Area-efficient HEVC core transform using multi-sized and reusable DCT architectures

This paper presents an area-efficient and multi-sized DCT architecture for HEVC application. We exploit the commonality in the arithmetic units to increase the hardware reusability as well as reducing the hardware cost. To do so, the multiplexed-multiple constant multiplication (Mux-MCM) problem is used so that the additions required for different constants are time-multiplexed to reuse the same adders in a unified circuit. We develop two efficient 1D-DCT architectures. The first architecture computes different transform sizes ranging from 4 × 4 to 32 × 32 and consumes the lowest hardware cost amongst the existing DCTs. The second architecture can process any combination of transform sizes and offers two options for designers: (1) The first option provides an area-efficient folded 2-D DCT capable of processing 60 fps of 4 K resolution. (2) The second one, which is based on the unfolded structure, achieves the double throughput and can process 60 fps of 8 K, at the expense of higher area overhead. The synthesis results for 90-nm technology show that the number of arithmetic units of the proposed architectures decreases remarkably as well as yielding around 36% and 67% reduction in area consumption and area-delay-product (ADP), respectively, compared to that of the other architectures.