Architectures and applications of high-speed vision

被引:0
|
作者
Yoshihiro Watanabe
Hiromasa Oku
Masatoshi Ishikawa
机构
[1] University of Tokyo,
[2] Gunma University,undefined
来源
Optical Review | 2014年 / 21卷
关键词
visual feedback; dynamics matching; target tracking; gesture recognition; three-dimensional sensing; dynamic image control; intelligent robot;
D O I
暂无
中图分类号
学科分类号
摘要
With the progress made in high-speed imaging technology, image processing systems that can process images at high frame rates, as well as their applications, are expected. In this article, we examine architectures for high-speed vision systems, and also dynamic image control, which can realize high-speed active optical systems. In addition, we also give an overview of some applications in which high-speed vision is used, including man-machine interfaces, image sensing, interactive displays, high-speed three-dimensional sensing, high-speed digital archiving, microvisual feedback, and high-speed intelligent robots.
引用
收藏
页码:875 / 882
页数:7
相关论文
共 50 条
  • [1] Architectures and Applications of High-Speed Vision
    Watanabe, Yoshihiro
    Oku, Hiromasa
    Ishikawa, Masatoshi
    [J]. OPTICAL REVIEW, 2014, 21 (06) : 875 - 882
  • [2] DFE architectures for high-speed backplane applications
    Li, M
    Wang, S
    Kwasniewski, T
    [J]. ELECTRONICS LETTERS, 2005, 41 (20) : 1115 - 1116
  • [3] High-speed memory architectures for multimedia applications
    Oshima, Y
    Sheu, BJ
    Jen, SH
    [J]. IEEE CIRCUITS & DEVICES, 1997, 13 (01): : 8 - 13
  • [5] Special Issue on High-Speed Vision and its Applications
    Ishikawa, Masatoshi
    Ishii, Idaku
    Oku, Hiromasa
    Namiki, Akio
    Yamakawa, Yuji
    Hayakawa, Tomohiko
    [J]. JOURNAL OF ROBOTICS AND MECHATRONICS, 2022, 34 (05) : 911 - 911
  • [6] A novel high-speed architecture for machine vision applications
    Farroha, BS
    Deshmukh, RG
    [J]. MACHINE VISION APPLICATIONS, ARCHITECTURES, AND SYSTEMS INTEGRATION V, 1996, 2908 : 43 - 49
  • [7] Multistage pipelined architectures of Piccolo cipher for high-speed IoT applications
    Mishra, Shubham
    Mishra, Zeesha
    Panigrahy, Saroj Kumar
    Acharya, Bibhudendra
    [J]. International Journal of High Performance Systems Architecture, 2022, 11 (02): : 96 - 104
  • [8] HIGH-SPEED DRAMS WITH INNOVATIVE ARCHITECTURES
    OHSHIMA, S
    FURUYAMA, T
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1994, E77C (08) : 1303 - 1315
  • [9] Trends in high-speed DRAM architectures
    Kumanoya, M
    Ogawa, T
    Konishi, Y
    Dosaka, K
    Shimotori, K
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 1996, E79C (04) : 472 - 481
  • [10] PARALLEL ARCHITECTURES FOR HIGH-SPEED MULTIPLIERS
    MADEN, B
    GUY, CG
    [J]. 1989 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, 1989, : 142 - 145