A fog-based anonymous authentication scheme with location privacy for wireless body area network with FPGA implementation

被引:0
|
作者
Arun Sekar Rajasekaran
M. Azees
机构
[1] KPR Institute of Engineering and Technology,Department of ECE
[2] VIT-AP University,School of Computer Science and Engineering
[3] Inavolu,undefined
[4] Beside AP Secretariat,undefined
关键词
Authentication; Confidentiality; Integrity; Privacy;
D O I
暂无
中图分类号
学科分类号
摘要
In Healthcare 4.0, Wireless Body Area Networks (WBAN) takes place a major role in gathering real-time data of patients. The gathered real-time medical data is transferred through an insecure channel which may lead to several security attacks. To secure from these attacks, the methodology adopted in this work involves the use of a lightweight secure anonymous authentication scheme with location privacy and the implementation of a WBAN system using a cadence tool. Moreover, the methodology encompasses several stages, including initialization, registration, authentication, and location privacy. Further, the study adopts a systematic approach to address key challenges, such as integrity, privacy, security, and non-repudiation. The hypothesis underlying this research is that WBANs can provide accurate and real-time healthcare monitoring using an anonymous authentication scheme and validated by using cadence software. In this work, a digital signature-based cryptographic technique is used to verify the authenticity and integrity of the messages. The security analysis section proves that the system is efficient in resisting different security attacks. Though there are several existing works related to authentication, the proposed protocol is very efficient in terms of performance analysis parameters which are validated using Cygwin software. Computational cost is diminished by 13% and communication overhead is reduced by 32% when compared to the relevant recent works. Additionally, a practical hardware approach is designed using a Verilog Hardware description language and implemented in hardware on an Arty A7-100 SoC FPGA (Silicon on Chip Field Programmable Gate Array) Development board where the number of bonded IOBs utilization is only 10% and lastly synthesized using a Cadence tool with CMOS GPDK 90 nm technology.
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页码:1 / 13
页数:12
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