Power-aware sourse feedback single-ended 7T SRAM cell at nanoscale regime

This article presents a low power and highly stable source feedback SE7T (single-ended 7T) SRAM cell. Using Monte-Carlo simulations critical design metrics of proposed SE7T SRAM cell are estimated and the estimated results are compared with that of conventional 6T SRAM cell and conventional 7T SRAM cell (CONV7T). The proposed source feedback single Ended (SE7T) SRAM cell achieves 8.6 ×/12.5 × and 1.2 ×/5.3 × lower write power and hold power as compared to CONV6T/CONV7T respectively. The proposed bitcell takes 1.3 × longer but 1.3 × less Read Access Time (TRA) as compared to CONV6T and CONV7T at 200 mV respectively. The proposed bitcell also provides 1.67 × and 1.07 × higher read stability and write ability as compared to 6T SRAM Cell.