An Efficient Logic Equivalence Checker for Industrial Circuits

被引：3

作者：

Jaehong Park

Carl Pixley

Michael Burns

Hyunwoo Cho

机构：

[1] IBM,

[2] Motorola Inc.,undefined

[3] Samsung Electronics Inc.,undefined

[4] Kihung,undefined

来源：

Journal of Electronic Testing | 2000年 / 16卷

关键词：

functional verification; equivalence; logic checking; formal; BDD; ATPG; combinational; MET;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

We present our formal combinational logic equivalence checking methods for industry-sized circuits. Our methods employ functional (OBDDs) algorithms for decisions on logic equivalence and structural (ATPG) algorithms to quickly identify inequivalence. The complimentary strengths of the two types of algorithms result in a significant reduction in CPU time. Our methods also involve analytical and empirical heuristics whose impact on performance for industrial designs is considerable. The combination of OBDDs, ATPG, and our heuristics resulted in a decrease in CPU time of up to 80% over OBDDs alone for the circuits we tested. In addition, we describe an algorithm for automatically determining the correspondence between storage elements in the designs being compared.

引用

页码：91 / 106

页数：15

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