共 50 条
- [3] Design of high performance CMOS current-mode winner-take-all circuit [J]. 2003 5TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2003, : 568 - 572
- [6] Enhanced modular CMOS current-mode winner-take-all network [J]. ICECS 96 - PROCEEDINGS OF THE THIRD IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS, VOLS 1 AND 2, 1996, : 402 - 405
- [9] High-Precision Current-Mode Loser-Take-All & Winner-Take-All Circuits [J]. 2011 INTERNATIONAL CONFERENCE ON FUZZY SYSTEMS AND NEURAL COMPUTING (FSNC 2011), VOL I, 2011, : 37 - 40
- [10] A Current-Mode Hysteretic Winner-take-all Network, with Excitatory and Inhibitory Coupling [J]. Analog Integrated Circuits and Signal Processing, 2001, 28 : 279 - 291