An analog circuit analysis method by node elimination

被引:0
|
作者
Guoyong Shi
机构
[1] Shanghai Jiao Tong University,Department of Micro/Nano Electronics, School of Electronic Information and Electrical Engineering
关键词
Analog integrated circuit (IC); Driving point impedance (DPI); Node elimination; Signal-flow graph (SFG); TIme-Constant Equilibration Reduction (TICER);
D O I
暂无
中图分类号
学科分类号
摘要
This paper introduces a node elimination method for analog circuit analysis. It is useful for manually deriving the transfer functions of small active circuit cells in analog integrated circuit design. This method is essentially a variant of Gaussian elimination and can be established based on the driving point impedance method. By successively reducing the circuit size, a circuit can be easily solved as soon as all internal nodes are eliminated. Examples are provided to illustrate the analysis steps.
引用
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页码:247 / 252
页数:5
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