Design of area and energy-efficient digital CMOS FIR filters with approximate adder circuits

This paper proposes the use of alternative approximate adders for fully parallel energy-efficient complementary metal–oxide–semiconductor (CMOS) finite impulse response (FIR) filters design. The filters to be approximated are first optimized for low power by a state-of-the-art multiplier-less multiple constant multiplication algorithm. We further evaluate magnitude error and accuracy for different state-of-the-art approximate adder techniques plus the truncation of adders, and validate this with 16-bit audio signals histogram analysis. Once the approximation is performed for all the filters, we evaluate the signal-to-noise ratio (SNR) response for ten recorded audio signals. All precise and approximate filters benchmark cases with different SNR targets are synthesized and mapped onto a 45 nm CMOS PDK for full ASIC implementation. Energy-efficiency results show that our proposed approximate filters, subject to a 50 dB Signal to Noise + Distortion Ratio required floor, reduce on average the energy per filtered sample by up to 24.8 and 23.8 % for 100 and 10 MHz circuit operation, respectively.