Circuit simulation of threshold-voltage degradation in a-Si:H TFTs fabricated at 175 °C

被引：15
|
作者：
Shringarpure, Rahul [1 ]
Venugopal, Sameer
Li, Zi
Clark, Lawrence T.
Allee, David R.
Bawolek, Edward
Toy, Daniel
机构：
[1] Arizona State Univ, Dept Elect Engn, Tempe, AZ 85287 USA
[2] Arizona State Univ, Flexible Display Ctr, Tempe, AZ 85284 USA
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2007年 / 54卷 / 07期
关键词：
circuit simulation; display technology; hydrogenated amorphous silicon thin-film transistor (a-Si : TFT); SPICE; threshold-voltage degradation;
D O I：
10.1109/TED.2007.899667
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a novel approach to modeling gate bias-induced threshold-voltage (V-th) degradation in hydrogenated amorphous silicon thin-film transistors (TFTs). The V-th degradation model is added to the SPICE 3.0 TFT device model to obtain a composite model and is verified by comparing the simulated Vth shift with measured data in a TFT latch circuit.
引用
收藏
页码：1781 / 1783
页数：3
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