System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip (December 2002)

被引：52
|
作者：
Givargis, T [1 ]
Vahid, F
Henkel, J
机构：
[1] Univ Calif Irvine, Dept Informat & Comp Sci, Irvine, CA 92697 USA
[2] Univ Calif Irvine, Ctr Embedded Comp Syst, Irvine, CA 92697 USA
[3] Univ Calif Riverside, Dept Comp Sci & Engn, Riverside, CA 92521 USA
[4] NEC USA, C&C Res Labs, Princeton, NJ 08540 USA
来源：
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | 2002年 / 10卷 / 04期
基金：
美国国家科学基金会;
关键词：
design space exploration; low-power design; Pareto-optimal configurations; platform-based design; system-on-a-chip (SOC) design;
D O I：
10.1109/TVLSI.2002.807764
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
dIn this work, we provide a technique for efficiently exploring the power/performance design space of a parameterized system-on-chip (SOC) architecture to find all Pareto-optimal configurations. These Pareto-optimal configurations will represent the range of power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application that is mapped on the SOC architecture. Our approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. We have successfully applied our technique to explore Pareto-optimal configurations of our SOC architecture for a number of applications.
引用
收藏
页码：416 / 422
页数：7
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