High-speed Energy-efficient 5:2 Compressor

Multipliers are important components that dictate the overall arithmetic circuits' performance. The most critical components of multipliers are compressors. In this paper, a new 5: 2 compressor architecture based on changing some internal equations is proposed. In addition, using an efficient full-adder (FA) block is considered to have a high-speed compressor. The number of transistors in the proposed design is less than the best existing 5: 2 compressor architectures. Three 5: 2 compressors are considered for comparison. The proposed architecture is compared with the best existing designs presented in the state-of-the-art literature in terms of power, delay and area. Architectures are simulated in 90-nm CMOS technology under 1 V supply voltage. The simulation results show that the proposed compressor improves power and delay by 24.59% and 18.54% respectively, compared to two of the best existing architectures. In addition, voltage scaling and temperature analysis show that the proposed architecture outperforms the other designs from power-delay product (PDP) point of view in comparison to the aforementioned designs.