Towards Purposeful Design Space Exploration of Heterogeneous CGRAs: Clock Frequency Estimation

被引：0

作者：

Wolf, Dennis Leander ^{[1
,2
]}

Spang, Christoph ^{[3
]}

Hochberger, Christian ^{[1
,2
]}

机构：

[1] Tech Univ Darmstadt, Dept Elect Engn, Darmstadt, Germany

[2] Tech Univ Darmstadt, Informat Technol Comp Syst Grp, Darmstadt, Germany

[3] Tech Univ Darmstadt, Dept Comp Sci, Embedded Syst & Applicat Grp, Darmstadt, Germany

来源：

PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC) | 2020年

关键词：

D O I：

暂无

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Coarse Grained Reconfigurable Arrays become increasingly popular. Besides research on scheduling algorithms and microarchitecture concepts, the use of heterogeneous structures can be a key approach to exploit their full potential. Unfortunately, a purposeful design space exploration of CGRAs is not trivial, since one needs to know the clock frequency of the resulting hardware implementation. This paper discusses challenges and a statistical approach to maximum clock frequency estimation of heterogeneous CGRAs with an irregular interconnect on FPGAs. The presented approach allows estimation with a maximum error of 8.8 - 17.4 % and a mean error of only 1.9 - 4.6 %.

引用

页数：6

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