Formal Verification for Validation of PSEEL's PLC Program

被引:3
|
作者
Niang, Mohamed [1 ,2 ]
Philippot, Alexandre [1 ]
Gellot, Francois [1 ]
Coupat, Raphael [2 ]
Riera, Bernard [1 ]
Lefebvre, Sebastien [2 ]
机构
[1] Univ Reims Champagne Ardenne Moulin Housse, CReSTIC EA3804, BP 1039, F-51687 Reims 2, France
[2] Soc Natl Chemins Francais, IP TE CES Direct Ingn, 6 Ave Francois Mitterrand, F-93574 La Plaine St Denis, France
关键词
Model-checking; Recipe Book; Factory Tests; Systems Engineers; Railways; Safety;
D O I
10.5220/0006418705670574
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
In order to keep its leadership in French rail market and to improve work conditions of its systems engineers during automation projects, the SNCF (French acronym for National Society of French Railways) wants to develop solutions increasing the productivity. One of these improvements focuses on the current methodology used by systems engineers to verify and validate PLC programs of electrical installations. This task remains one of the most important during an automation project because it is supposed to ensure installations safety, but it must be optimized. Through an industrial thesis financed by SNCF, the aim of this research project is to improve this method and reduce time validation of programs by providing a tool which will help systems engineers to verify and validate quickly and automatically PLC programs during any automation project, not necessarily during factory tests but directly from their office.
引用
收藏
页码:567 / 574
页数:8
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