Explicit Analytical Current-Voltage Model for Double-Gate Junctionless Transistors

被引：22
|
作者：
Hwang, Byeong-Woon [1 ]
Yang, Ji-Woon [2 ]
Lee, Seok-Hee [1 ]
机构：
[1] Korea Adv Inst Sci & Technol, Dept Elect Engn, Taejon 305701, South Korea
[2] Korea Univ, Dept Elect & Informat Engn, Sejong 339701, South Korea
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2015年 / 62卷 / 01期
基金：
新加坡国家研究基金会;
关键词：
Compact modeling; junctionless (JL) transistor; multigate MOSFET; variability; CIRCUIT SIMULATION; MOSFET MODEL;
D O I：
10.1109/TED.2014.2371075
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
An explicit analytical model for long-channel double-gate junctionless transistors is presented in each operation mode: 1) full depletion; 2) partial depletion; and 3) accumulation. The proposed model calculates potentials, electric fields, mobile charges, and drain current without any implicit function or special functions. The results obtained with the proposed model agree well with the results obtained with a 2-D technology computer-aided design simulation in all modes of operation and for various device structures. Furthermore, a physical insight is provided into reducing variability using the threshold voltage model.
引用
收藏
页码：171 / 177
页数：7
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