Compact high gain CMOS op amp design using comparators

被引：0

作者：

Purcell, J ^{[1
]}

Abdel-Aty-Zohdy, HS ^{[1
]}

机构：

[1] Oakland Univ, Dept Elect & Syst Engn, Microelect Syst Design Lab, Rochester, MI 48309 USA

来源：

40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2 | 1998年

关键词：

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper discusses the design of a high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 mu m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of +/-2.5V. It occupies an area of 113 mu m x 474 mu m.

引用

页码：1050 / 1052

页数：3

共 50 条

[1] Compact high gain CMOS op amp design using comparators
Abdel-Aty-Zohdy, HS
Purcell, J
[J]. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 1999, 19 (02) : 139 - 144
[2] Compact High Gain CMOS Op Amp Design using Comparators
Hoda S. Abdel-Aty-Zohdy
John Purcell
[J]. Analog Integrated Circuits and Signal Processing, 1999, 19 : 139 - 144
[3] Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback
Subhra Chakraborty
Abhishek Pandey
Vijay Nath
[J]. Microsystem Technologies, 2017, 23 : 541 - 552
[4] Ultra high gain CMOS Op-Amp design using self-cascoding and positive feedback
Chakraborty, Subhra
Pandey, Abhishek
Nath, Vijay
[J]. MICROSYSTEM TECHNOLOGIES-MICRO-AND NANOSYSTEMS-INFORMATION STORAGE AND PROCESSING SYSTEMS, 2017, 23 (03): : 541 - 552
[5] A CMOS low-voltage, high-gain op-amp
Lu, GN
Sou, G
[J]. EUROPEAN DESIGN & TEST CONFERENCE - ED&TC 97, PROCEEDINGS, 1997, : 51 - 55
[6] A High-Gain, Low-Power CMOS Op Amp Using Composite Cascode Stages
Comer, David J.
Comer, Donald T.
Singh, Rishi Pratap
[J]. 53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 600 - 603
[7] A negative conductance voltage gain enhancement technique for low voltage high speed CMOS op amp design
Yan, J
Geiger, RL
[J]. PROCEEDINGS OF THE 43RD IEEE MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS I-III, 2000, : 502 - 505
[8] Implementation of High Gain and High Bandwidth CMOS Op-Amp using 180nm SCL Technology
Kalita, Deepjyoti
Sharma, Hrishita
[J]. 2022 IEEE 19TH INDIA COUNCIL INTERNATIONAL CONFERENCE, INDICON, 2022,
[9] A low voltage high unity-gain bandwidth CMOS OP-AMP
Yu, CM
Lin, ZM
Chen, JD
[J]. PROCEEDINGS OF THE 2004 IEEE ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1 AND 2: SOC DESIGN FOR UBIQUITOUS INFORMATION TECHNOLOGY, 2004, : 45 - 48
[10] Design of OP-AMP using CMOS Technology & Its Application
Katara, Arun
Balwani, Riya
Wagh, Priya
Salankar, Prachi
[J]. 2016 INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONICS, AND OPTIMIZATION TECHNIQUES (ICEEOT), 2016, : 3633 - 3636

← 1 2 3 4 5 →