FPGA-Based Optimized Design of Montgomery Modular Multiplier

This brief introduces FPGA-based optimized implementation of Montgomery Modular Multiplier (MMM) architecture. The novel architecture of the proposed design enhanced the maximum frequency of the design and also the occupied area on the targeted FPGA. A Xilinx Virtex-6 FPGA implementation of the proposed architecture comparing with other related designs revealed that, our design occupies the smallest area, and the efficiency is enhanced in the range between 1.2 to 11.7 times the efficiency of other relevant designs. The proposed design is implemented as a modular multiplier for lightweight elliptic curve cryptography (ECC) over general GF(p). The proposed architecture is targeted the hardware implementation of lightweight cryptographic modules used on the System on Chip (SoC) and Internet of Things (IoT) devices.